SAJESM - IJTAG-1149.1-2013 Flow for Embedded IP

1149.1-2013 has been enhanced to standardize the access and interface of embedded Intellectual Property (IP). (Similar to IEEE 1687 in many areas with many of the same goals) 1149.1-2013 defined two new languages:  structural documentation in Boundary-Scan Description Language (BSDL) or BSDL "User Package" files using new attributes, and procedural documentation in a set of Procedural Description Language (PDL) procedures. PDL defines the stimulus and reading the response directly to and from the IP block. Using these two languages, 1149.1-2013 can define complex reconfigurable access networks, how the IP are connected to the network, and describe the IP interface.

SiliconAid has a Full Suite of tools which have been used by key development partners using 1149.1-2013. This robust suite of products are now available as a standard product. Our 1149.1-2013 Tool Suite supports the latest BSDL and PDL syntax.

The SAJE 1149.1-2013 IP Flow enables IP Providers, SOC designers and Integrators,  Verification engineers, Validation engineers, Test and Product engineers, and Failure Analysis engineers to develop and leverage the new 1149.1-2013 standard. Our easy to use flow produces a self-checking testbench for simulation and also supports downstream formats to support Test ATE, Board Test, and System Testing.

The SAJE tool suite can utilize compliant IP or analyze compliant 1149.1-2013 SOCs from all vendors. Compliant IP from multiple vendors or EDA companies is not problem.

SiliconAid IJTAG Consulting Services focused on helping make your IP compliant and any other IJTAG related custom work required to optimize your IJTAG solution.

 

JTSTM - (JTAG /  IJTAG Insertion)  - Creates all the structures required for IJTAG compliant designs. Compatible with any compliant JTAG controller from any EDA vendor or custom design. User controlled SIB locations and IJTAG network creation. Creates all connections to and from user selected IP and generates chip level ICL file. Supports simple to complex user specified IJTAG structures including multiple levels of IJTAG hierarchy.

Coming Soon!

JTVTM - 1149.1-2013 : This is an optional feature that can be added to our flagship JTV product to fully support all the new features of 1149.1-2013 including IP embedded testing. This enables the Automatic Semantic & Syntax checking, Verification, and Pattern Generation of patterns using PDL. JTV also will traverses the network(s) to verify all network possibilities and generates the associated tests.

 

JTNTM : Automatically & Intuitively draws the embedded IP network graphically. Allowing the user to visualize the network, select instruments for pattern generation, select different tests, analyzes and optimizes the network, and intelligently retargets patterns to the chip level. JTN provides the user with the flexibility to configure the network on the fly for greater and faster debug.

 

JTDTM : Interactive and intuitive JTAG debugger that drives hardware via the JTAG interface. JTD will interface with JTN to instantly apply new IJTAG patterns to the Chip JTAG interface.


IJTAG Consulting Services : (IJTAG-1687 and IJTAG-1149.1-2013) Leveraging over 15 years of DFT consulting on your IJTAG related challenges. Senior Engineers that know and understand IJTAG networks and architectures. Providing world-class services on your custom IJTAG requirements. Assisting in generating IJTAG related BSDL additions and PDL for in-house or third-party IP and much more.