Sponsored By

 

 

 
Hosted By


               

When : May 30
th & 31
st, 2007

Where : Omni SouthPark Hotel, Austin TX

Who Should Attend : Anyone interested in learning more about DFT methods for practical real world chip applications. DFT engineer, Test/Product Engineers, FA engineers, middle to upper managers.

SORRY - Class is FULL

PRE-REGISTRATION has ended for the Technical Day (May 31st)
ON-SITE Registration opens at 8AM - $20 door fee

 Event Description

This 2 day DFT event will be held at the Omni SouthPark Hotel. This event will consist of a day of a DFT class and a day open technical day. The technical day will be a mix of vendors and guest presenters. The technical day is FREE and is open to all when you pre-register on this web site. You can register for the conference now. Class registration is open on a first come first serve bases.

FREE DFT Class (May 30th)

Give by three or four Senior DFT engineer (Al Crouch, Carl Barnhart, Jim Johsnon). This FREE one day class will cover DFT techniques and advanced DFT topics. A full outline of the class will be added to the website in the next week or so.

FREE Technical DFT Day (May 31st)

The technical day is a FREE day to any and all web-registered attendees (
before May 25th). DFT and test engineers from the semiconductor industry and the EDA community will be presenting. The day will start with a Key Note Speaker followed by 6 to 8 technical talks and presentations. We expect to exceed over 150 attendees for the final day of the event. DFT Companies will also be setting up small booth demonstrations in the hallway just outside of the main conference hall. See below for the Agenda!

                                                            

MAY 31st, 2007                                                                     

8:00 - 8:30 On site Registration (coffee provided)
8:30 - 8:40 Welcomes and introductions
8:40 - 9:10 Key Note Address - Prof. Hank Walker (Texas A&M)

Session 1 – Advanced DFT Techniques   
9:10 - 9:55 - Presentation 1 -
Steve Sunter (LogicVision)
        Title -
BIST Techniques for Delay and Jitter in Nanometer Technology ICs
9:55 - 10:40 - Presentation 2 - Kedarnath Balakrishnan (AMD)
        Title - Transition Testing Data Volume Reduction Using Test Point Insertion at RTL
10:40 - 11:15  B R E A K
Session 2 – DFM & Yield Learning          

11:15 - 12:00 - Presentation 3 - Grzegorz Mrugalski (Mentor Graphics)

       
Title - Low Power Embedded Deterministic Test
11:45 - 1:30 LUNCH - Free lunch
1:30 - 2:15 - Presentation 4 - Mathias Kamm (Cisco Systems)

        Title -
Reducing ASIC NTFs
Session 3 – DFT related topics   
2:15 - 3:30 - Presentation 5 -
Calvin Cheung (ASE)
        Title -
Stacked - Die testing
3:30 - 3:45  B R E A K
3:45 - 4:30 - Presentation 6 -
Krishna Srinivasan (Austin Ventures)
        Title -
VCs and the outlook for the Semiconductor industry
4:30 - 5:30 - Panel Discussion                       Referee: Jim Johnson
4:30  - 5:30 Happy Hour during Panel

Vendor Booths open from 8:30am - 6pm


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