Design For Test (DFT) Services - Implementation

Scan Insertion, Add/Optimize Test Control Logic, and ATPG - Vector Generation

SiliconAid Solutions Inc. can provide the optimal scan implementation to obtain the highest possible test coverage at the lowest possible cost. Full scan, Partial scan or a combination of both could be used depending on the customers requirements and objectives. A full set of DFT specific DRC(Design Rules Checks) are run to help determine any issues as early in the process as possible.

Test Synthesis is the modification of the design to add scan circuitry. Some of the steps included in this phase of the development are:
  • DFT Design Rules Checking
  • Scan Cell Substitution
  • Scan Chain Connection
  • Control Logic Insertion
  • Optimal Scan Chain Partitioning (# of chains,# of flops/chain)

ATPG Vector Generation is the creation of patterns for manufacturing testing. Some of the steps in this phase of the development are:
  • Scan patterns to achieve high test coverage
  • IDDQ Pattern Generation
  • "AT SPEED" Pattern Generation
  • Resimulation/Verification of all patterns

Additional Challenges may include:
  • Mutliple Clock Domains
  • Chip level Integration
  • Clock Skew issues
  • Test Point Insertion
  • Power Management during scan operation
  • Scan Chain Optimization based on Physical Placement

Memory BIST Generation

Today, most devices and SOC's contain some form of embedded memory. Memory Built In Self Test (BIST) is a very efficient way to test these memories with a relatively low area and design impact.

We can analyze your specific architecture and objectives to determine how the memory BIST should be designed and implemented.

We will use our expertise to identify:
  • Which Algorithm(s) should be used?
  • Can Memory BIST controllers be shared?
  • What debugging features are required?
  • How to do test "AT SPEED"?
  • How to obtain a minimal area and timing impact?
  • How to control the Memory BIST?

SiliconAid Solutions has extensive experience generating many different types of Memory BIST solutions. We can generate RTL level synthesizable code for the Memory BIST logic and controller(s). Our team can also help you integrate BIST logic into your design.

Logic BIST Insertion

Logic Built In Self Test (BIST) leverages a scan based design to minimize the requirements for external test stimulus or capture.

Logic BIST should be considered on :
  • Designs with large vector requirements
  • Designs which want to utilize less expensive ATE equipment
  • Designs with minimal or no pins available for test purposes
  • Devices which need to execute on-board system tests

Our team has experience in Logic BIST design and implementation. We can generate RTL level synthesizable code for the Logic BIST logic and controller(s). Our team can also help you integrate BIST logic into your design.

JTAG Generation

IEEE 1149.1 standard also referred to as JTAG or Boundary Scan is primarily for board level testing. JTAG is commonly used and can be implemented with additional functionality to control special test modes.

SiliconAid Solutions can implement a 1149.X and all associated standards compliant design and customize it for your specific design and testing requirements. The JTAG controller will be fully verified to operate correctly.

Fault Simulation and Grading

SiliconAid Solutions can take existing scan patterns or functional patterns and Fault Simulate them to determine the level of test coverage they provide. We can also generate additional patterns to improve the overall test coverage of the device.

We will produce a test coverage report describing the scan and functional patterns executed, the coverage for each pattern set, and an overall chip coverage numbers.

Manufacturing Test Program Debug Assistance and Failure Analysis Assistance

SiliconAid Solutions can reformat failing ATE vector data and help pin point the area and possible gates causing the failure. This type of fault isolation is invaluable in the debugging and characterization phases of the product life cycle.

While we are not test engineers, we are familiar with ATE architectures. We can work with the test engineers to help identify and correct issues.