SAJESM - JTD Overview
SAJE JTDTM has been developed to be an interactive JTAG debugger for chip debug and troubleshooting on real hardware. Easy and intuitive to use, JTD can read in patterns from multiple sources and drive the corresponding data out of the USB port. JTD can capture actual data from the device and compare it to expected data.
Developed to have the same basic look and feel as a simple ATE tester to control and observe data.
JTD has many of the same features: Run, Step, Stop on Vector, Stop on Fail, and more...
Drives JTAG hardware plus optional GPIO pins
Supports 1149.1, 1149.6, and IJTAG
Multiple Hardware Supported
Compares Expected TDO values
Supports multiple file formats
Supports most features of an expensive ATE
Windows and Linux platforms
Perfect for Debug, Failure Analysis , First silicon validation, and more...
Special modes have been built into JTD to allow leveraging of design data and information in the BSDL file. This data is automatically displayed with intuitive graphical windows. These windows are synchronized to the active vector and change dynamically as you step through the vectors.
JTD has a unique capture mode to allows the user to run a test and specify internal functional registers to capture. JTD can automatically generate the waveforms of those internal registers. Giving the user the ultimate logic analyzer function displayed in an easy to read waveform.
JTD can support multiple hardware from several vendors. SiliconAid now has newly developed hardware called the JitterBugTM.
The JitterbugTM is a high speed USB JTAG port connector, developed to support the SiliconAid SAJESM Tool Suite. Any device, board or system, with a standard JTAG or IJTAG interface, and associated test suites that can be controlled through the JTAG port, are manageable by the Jitterbug USB hardware.