Design For Test (DFT) Services - Initial Phases
DFT Evaluation and AssessmentWe analyze your design to determine the testability of the design. How good is your test quality? How could it be made better? We identify areas of low test coverage and focus on what techniques would increase testability. The DFT strategy and the design flow is also reviewed at a high level.
Some common steps that an evaluation would include are:
- Review the DFT strategy used
- Review of the design
- Identify areas of low test coverage
- Identifying DFT hard to test logic or structures
- Uncontrolled or Unobserved logic
- Identify additional DFT techniques for untested logic
- Make changes to temporary design
- Verify impact of changes
- Generate a DFT Evaluation Report
Lastly, we generate an evaluation report. This report will include a summary of all the issues and how they are affecting the test coverage. It will also give suggestions on how to resolve these issues. It will provide estimates on the impact to the design and test coverage the suggestion(s) would make.
DFT Methodology DevelopmentDFT Methodology can be developed in several approaches depending upon the customer needs and requirements. We can work with your team in an advisory capacity to enhance and augment your team. We can also do a turn key solution that develops your DFT methodology and flow around your specific design flow and goals.
Since we are an indepenent company, we can offer an unbiased opinion for the optimal flow for your goals and cost objectives.
An evaluation of the specific cost objectives and goals will be reviewed to make the design impact vs DFT and test trade-offs. Things like expected manufacturing volume and device size may influence the DFT flow. A complete flow can be developed and tested to make sure the flow generates all the correct views and files required to fit seamlessly into your design environment.
The flow can then be customized and automated to guarantee repeatable and reliable results.
DFT AutomationSiliconAid Solutions can automate your flow to execute with very little interaction required in many cases. This allows a non-DFT expert to execute some or most of the DFT steps which could include scan insertion, ATPG, MBIST insertion, and more.
Several types of scripts could be utilized depending upon the design flow and tools available. (DC shell scripts, PERL, C or C++, TCL, C-shell scripts)
For more generic flows, a web based custom interface could be generated to control the DFT steps.
Design vs Test Time & DFT Trade-offsDepending upon the customer objective, different trade-offs might be made for your the DFT strategy.
- Should you add a few more gates to increase test coverage?
- Full scan vs Partial scan?
- Should you add a few more gates to reduce tester time?
- Is timing impacted by your DFT methodology?
- How does improving test coverage affect your customer returns?
- Can DFT help you reduce your overall time-to-market and how?
- Does DFT help you reduce your chip verification time?
- Can DFT help you get your chip qualified faster?
- Does utilizing DFT help you debug final silicon?
ATPG Library GenerationSeveral major DFT software vendors require a custom library or modified library views for DFT. We are well versed in generating these required libraries. We can use the customer's golden verilog model or VHDL model to generate and/or verify the ATPG models. We verify by simulation that the models function correctly and match the golden models.
Companies that supply libraries or memory models may also require verification of the models supplied.
Any mismatch between the simulation library and the DFT library can cause patterns to be non-functional further down the product development cycle.