SAJE^SM - JTV Overview

SAJE JTV^TM has been developed over a twenty four year period by JTAG practitioners and used on thousands of production devices. JTV is protected with a US Patent. JTV uses a standards driven approach and is well suited for design flows in which the JTAG design is derived from earlier designs or synthesized from third-party tools. JTV serves as an independent verification tool to lower the risk of design-related defects.

• Supports 1149.1, 1149.6, and the new 1149.1-2013

• Supports IJTAG (1687)

• Semantic, Syntax Checking, and Compliance checking

• Ensures correct JTAG functionality on first-pass silicon

• Generates full self-checking verification testbench

• Generates STIL-formatted patterns for ATE test

• Complements all custom or EDA based JTAG flows

SAJE JTV provides a large robust suite of automatically generated tests to verify a JTAG implementation and the associated BSDL file. During the design phase, these tests support comprehensive design verification while eliminating the need to manually write unit tests or a verification testbench.

For silicon debug, JTV automatically generates high-quality production ready test patterns that facilitate first-silicon bring-up on debug stations or automatic test equipment (ATE).  During manufacturing, the tests provide high-quality data to drive yield analysis processes.