What The Press And Our Clients Are Saying
SiliconAid Solutions evolves support of IEEE 1687 and IEEE 1149.1-2013 Standards through Partnership with Ridgetop Group
Seattle, WA - October 20, 2014 -- SiliconAid Solutions, Inc., and Ridgetop Group., announced jointly today they have continued and expanded their partnership to enable support for the evolving industrial testability standards. Together they have developed a system to embed Ridgetop Group's SJ BISTTM board-level interconnection reliability monitor leveraging IEEE P1687 and IEEE 1149.1-2013 for intellectual property (IP). SJ BIST is a patented test IP product that detects interconnect faults between electronic devices, such as between integrated circuits (ICs) (including field programmable gate arrays [FPGAs] and systems-on-chip [SOCs]) and printed circuit boards (PCBs).
Ridgetop and SiliconAid applied SiliconAid's IEEE 1149.1-2013 and P1687 tool flows to develop compliant access to SJ BIST IP. Ridgetop continues to be a partner/customer to test and verify the SiliconAid IEEE 1149.1-2013 and P1687 flows. These adjusted implementations leverage enhanced automation, reuse, and debug capabilities of embedded chip instruments. In the past, a significant manual effort has been required to verify that embedded instruments were integrated and verified correctly in the customer design. Procedural Description Language (PDL) test pattern generation also had to be handled by the IP integrator. Using SiliconAidâ€™s new flow, a custom testbench can be generated automatically for every design in which the IP is used. Chip-level automated test equipment (ATE) patterns can also be generated automatically.
According to Andrew Levy, Ridgetopâ€™s VP of Business Development, "SJ BIST offers a solution for detecting troublesome intermittencies. We have worked with SiliconAid to take Ridgetop's SJ BIST Test IP Core through their P1687 IJTAG and boundary scan flows. Now that we have developed and demonstrated the ability to convert legacy patterns to PDL patterns that can be applied with these interface, our customers will enjoy even faster and more flexible deployment of SJ BIST to meet their needs for highly reliable boards and systems."
Jim Johnson, SiliconAid President and CTO, added, "We believe all IP providers will soon be delivering with support for both P1687 and 1149.1-2013 to enable IP reuse. The Plug and Play approach used by these new standards is a perfect fit for an IP provider like Ridgetop to improve quality and help the chip integrators. Utilizing these new standards will reduce the cost of integration, verification, and test pattern generation for the SOC companies using the IP. We support both of these two new standards and have a robust suite of tools to meet your needs for IP developers, SOC integrators, verification, manufacturing test, debug, and more."
Ridgetop Group and SiliconAid Solutions invite you to see a demonstration of the new capabilities and learn more at booth #604 at the International Test Conference in Seattle, Washington, October 21-23, 2014.
About Ridgetop Group, Inc.
Established in 2000, Ridgetop Group is a Tucson, Arizona-based firm that produces electronic solutions for harsh environments and challenging applications. The firm is qualified as an aerospace supplier under its AS9100C certification, and became a Category 1A Trusted Supplier under the DoD's Trusted Foundry Program in 2010. A privately held firm, Ridgetop operates two divisions in Tucson, and has a related subsidiary firm based in Europe near the European Space Agency facilities.
For more information, please contact firstname.lastname@example.org or visit Ridgetop's website at www.ridgetopgroup.com.
About SiliconAid Solutions
SiliconAid Solutions, Inc. is recognized as a leading provider of Design for Test Consulting and for world class chip-focused JTAG software solutions to validate, verify, and utilize IEEE JTAG-related industry standards. SiliconAid has corporate headquarters located in Austin, Texas and was founded in 2001. The Consulting Product Group has been recognized for comprehensive support of all standard EDA DFT solutions. The exhaustive chip-level validation, verification, and debug of IEEE JTAG-compliant implementations is based on over 20 years of testing and thousands of designs from multiple satisfied worldwide semiconductor companies.
For more information, please visit SiliconAidâ€™s website at www.SiliconAid.com.
SiliconAid Solutions, PLX Technology Partner on IEEE P1687-, IEEE 1149.1-2013-Based Test Development
AUSTIN, Texas â€“ September 3, 2013 â€“ SiliconAid Solutions, a privately held corporation and leader in chip-focused IEEE JTAG solutions and design for test (DFT) services, and PLX Technology, Inc., the global leader in PCI ExpressÂ® (PCIeÂ®) silicon and software connectivity solutions enabling emerging data center architectures, today announced a partnership to further the development of the companiesâ€™ solutions and the utilization of emerging IEEE JTAG-centric standards.
â€œPLX has successfully worked with SiliconAid to take our PCI Express switch with a high-speed SerDes instrument through the P1687 flow,â€ said Bala Ramakrishnan, PLXÂ® manager for DFT. â€œWe are pleased that all the patterns we have tried have worked using the SiliconAid products and appreciate the level of support we received throughout this experience.â€
Through its unique, industry-leading PCIe Gen3 switch technology, PLX is utilizing the emerging IEEE P1687 standard and leveraging the enhanced automation, reuse, and debug capabilities of embedded chip instruments. PLX is using SiliconAid IEEE 1149.1-2013 and P1687 preliminary tool flows, becoming a key partner in the testing and verification of these advanced EDA products.
In the past, a significant manual effort has been required to generate and then verify that embedded instruments were free of defects. A custom test-bench had to be generated, via a custom or I2C interface to confirm that the instrument functioned properly. There were not standard industry solutions available for this flow, which required even more manual effort and support concerns. In addition, a separate flow had to be used to generate manufacturing tests for the ATE environment.
PLX has been a user of the SiliconAid JTVTM tool, and with the addition of support for IEEE P1687 -- and the new IEEE 1149.1-2013 standards -- the flow for embedded instruments can now be automated and verified to be complaint.
â€œSiliconAid Solutions is proud to partner with companies like PLX Technology that have complex internal instruments that the new standards are designed to address,â€ said Jim Johnson, president and CTO, SiliconAid. â€œLeveraging these new standards to improve reuse, automate the flow, and verify compliance will dramatically reduce the cost of test and verification. SiliconAid has made it a priority to continue to develop and enhance our existing tools to be the best in its class.â€
About SiliconAid Solutions
SiliconAid Solutions, Inc. is recognized as a leading provider of Design for Test Consulting and for world class chip focused JTAG software solutions to validate, verify, and utilize IEEE JTAG related industry standards. SiliconAid has corporate headquarters located in Austin, Texas and was founded in 2001. The Consulting Product Group has been recognized for comprehensive support of all standard EDA DFT solutions. The exhaustive chip level validation, verification, and debug of IEEE JTAG compliant implementations is based on over 20 years of testing and thousands of designs from multiple satisfied worldwide semiconductor companies.
In addition to IEEE JTAG Standards centric solutions, SiliconAid has been an ongoing significant contributor to the definitions of the emerging P1687 IJTAG standard and 1149.1 JTAG standards and extensions developing working solutions tracking the evolving standards documentation. The P1687 and 1149.1 extensions are being created and standardized to expand the existing capabilities of JTAG standards, providing more support for transportable embedded IP and instruments.
Further information about SiliconAid Solutions and its products can be found on the internet at www.siliconaid.com.
Strategic relationship with SiliconAid extends ASSETâ€™s ScanWorks platform into chip test and verification
â€œThis is just the first step toward our vision of a continuous test flow
beginning at the chip level and extending to circuit boards and systems,â€ said
Glenn Woppman, president and CEO of ASSET. â€œBeyond this chip debugger that weâ€™ll
be integrating into the ScanWorks platform, we can see a time when extensive
chip tests can be re-used in board and system test, saving manufacturers
considerably on test development and shortening time-to-market. Weâ€™re also
excited about promoting SiliconAidâ€™s IEEE P1687 IJTAG tools. We want to
encourage the adoption of this emerging standard because we believe it will be
critical to the effective utilization of embedded instrumentation in future test
and measurement applications.â€
SiliconAidâ€™s JTDTM chip debugger, which will be integrated into ScanWorks immediately, is a robust real-time test and debug tool that can monitor structures inside chips and give visibility through an intuitive graphical interface to the engineer who is debugging the device. Although ASSET will initially resell SiliconAidâ€™s IEEE P1687 IJTAG synthesis (JTSTM) and verification (JTVTM) tools, future plans could call for these tools to be integrated into ScanWorks as well. JTSTM and JTVTM allow chip designers to automatically insert IJTAG capabilities into chips and subsequently verify the implementation. IEEE P1687 provides a standard interface to instrumentation embedded in chips.
â€œWe are excited about teaming up with ASSET to resell our tools and to help lead the industryâ€™s adoption of the IJTAG IEEE P1687 standard,â€ said Jim Johnson, president of SiliconAid. â€œThis standard is not just important for our two companies. It will be critical to the industry as embedded instrumentation proliferates in next-generation devices. Standards like P1687 enable a higher level of integration and automation, beginning with chip design and test, and then transitioning seamlessly into board test. Adding IEEE P1687 IJTAG tools into our suite is a natural next step for us to leverage our existing products and offer more value to our customers.â€
As part of the new relationship, the two companies agreed to do joint marketing. The first such activity will be the 2009 International Test Conference (ITC), Nov. 2-6 in the Austin Convention Center, Austin, TX. Both companies will have booths at this yearâ€™s ITC and ASSETâ€™s booth (No. 117) will feature a demonstration of SiliconAidâ€™s JTDTM debugger. In addition, ASSET will feature the JTDTM debugger at Productronica in Munich, Germany, Nov. 10-13 (Hall A1, Stand 470).
|Ridgetop Group Partners with SiliconAid Solutions on IEEE P1687 and IEEE 1149.1-2013 Standards|
August 27, 2013 -- Ridgetop Group, Inc. and SiliconAid Solutions, Inc. have partnered on emerging new industrial testability standards, IEEE P1687 and IEEE 1149.1-2013, and developed a system to embed Ridgetop Group's SJ BIST board-level interconnection reliability monitor. SJ BIST is a patented test IP product that detects interconnect faults between electronic devices, such as between FPGAs and printed circuit boards.
Ridgetop and SiliconAid applied SiliconAid's IEEE 1149.1-2013 and P1687 tool flows to develop compliant access to SJ BIST IP. Ridgetop has become a key driver partner/ customer to test and verify the SiliconAid IEEE 1149.1-2013 and P1687 flows. This new implementation leverages enhanced automation, reuse, and debug capabilities of embedded chip instruments. In the past, a significant manual effort has been required to generate and then verify that embedded instruments were integrated and verified correctly in the customer design. Test-pattern generation also had to be handled by the IP integrator. Using SiliconAid's new flow, a custom testbench can be generated automatically for every design in which the IP is used. Chip-level ATE patterns can also be generated automatically.
According to Andrew Levy, Ridgetop's Vice President of Business Development, "SJ BIST offers a solution in detecting troublesome intermittencies. We have worked with SiliconAid to take Ridgetop's SJ BIST Test IP Core through its P1687 flow. Now that we have developed and demonstrated the ability to convert legacy patterns to PDL patterns that can be applied with a P1687-compliant interface, our users will enjoy even faster and more flexible deployment of SJ BIST to meet their needs for highly reliable boards and systems."
Posted by: John Miklosz
AMDAMD Selects NEW JTAG Tool to Raise the Bar on Quality
Austin, Texas Ã¢â‚¬â€œ March 24th, 2006 Ã¢â‚¬â€œ SiliconAid Solutions, Inc. announced today that AMD (NYSE:AMD) has selected the SiliconAidÃ¢â‚¬â„¢s JTV (JTAG verification) tool.
The JTV tool provides a robust verification environment to ensure that your verilog design with JTAG and your BSDL (Boundary Scan Description Language) are fully consistent and comply with the IEEE 1149.1 and 1149.6 standards.
"SiliconAidÃ¢â‚¬â„¢s JTV JTAG tool has proven to be an extremely thorough and easy to use tool that provides excellent feedback. The transition was seamless and enabled us to continue important functionalities with virtually no interruption. As a result, we have a strong process driven by a great tool." - Tim Wood, AMD Fellow Complementary to an automated or custom JTAG design flow, JTV gives a quick, easy, and independent way to make sure your design is correct. JTV can output fault-simulated production test patterns and parametric tests. JTV is unique in its ability to verify that the chip design is JTAG-compliant and that the BSDL file accurately describes your JTAG design.
Mentor Graphics CorporationMentor Graphics Corporation (NYSE: MENT), one of the leaders in electronic design automation (EDA) has selected SiliconAid Solutions as its preferred DFT consulting subcontractor.
"We have worked with SiliconAid over several years successfully with multiple customers and projects. As a result of their senior DFT staff and dedication to quality and customer satisfaction, we call these guys firstÃ¢â‚¬Â says Scott Thompson, Mentor Consulting Manager for Yield Enhancement Services . "We leverage Jim and his team of experts to help augment existing staff on delivering world class DFT solutions to Mentor's customer base. We would recommend SiliconAid Solutions, Inc. DFT services to any company needing expert DFT advice and implementation assistance."
Intrinsity - Austin Texas"Intrinsity's 2GHz FastMATHÃ¢â€žÂ¢ Processor was completed on schedule employing simulation, verification and DFT design services from SiliconAid Solutions.", said Mike Becker, Director of Processor Design at Intrinsity Inc. "They quickly integrated into our team, added clear value and we wouldn't hesitate to use them again."
Analog Devices IncorporatedNEW JTAG Tool Improves BSDL Quality for Analog DevicesÃ¢â‚¬â„¢ Products
Austin, Texas Ã¢â‚¬â€œ June 28, 2005 Ã¢â‚¬â€œSiliconAid Solutions
Inc. announced today that Analog Devices, Inc. (ADI), a leading manufacturer of high-performance integrated circuits used in analog and digital signal processing applications, selected the SiliconAid SolutionsÃ¢â‚¬â„¢ JTV (JTAG verification) tool to enable high quality JTAG boundary scan functions and accurate BSDL files.
In the past, a significant manual effort has been required to generate and then verify the JTAG logic was correct. A custom testbench is generated to verify the boundary registers, TAP controller, and the associated connections. A BSDL file was generated but before JTV there was no formal or automated way to verify that the design actually matched the description in the BSDL file. Additionally, there was no automated way to verify that all modes of the JTAG where fully tested and that the device met the IEEE 1149.1 standard.
"JTV is a formal verification of the IEEE JTAG spec that saved the design teams using the tool countless months. As a result, the DSP and Digital Video Products that were developed with JTV have a high-quality JTAG boundary scan function and customers are seeing higher quality BSDL files for these products. JTV includes a boundary scan user's guide which is written in a clear and easy to understand style that teaches as well as guides the user about boundary scan design." - Luis Basto, Senior DFT lead.
"I've run thru all the boundary scan verification tests using SiliconAid's JTV tool. This is a very exhaustive list of about 20 separate tests that do everything one could consider with the boundary scan," continued Mr. Basto.
Fabless Mixed-Signal Start-UpOur company is a small startup company developing mixed signal system on chip (SoC) ASICS. We brought in SiliconAid Solutions, Inc. to help evaluate our present design and recommend possible DFT solutions to lower the overall product cost for current and future designs.
SiliconAid Solutions, Inc. quickly evaluated our design and generated a report to describe the benefits, cost trade-offs, and design impacts of adding DFT to our present device. Their willingness to work with us and tailor a level of involvement that fits our needs was a big plus. Although we do not have dedicated DFT capability right now we expect to develop it and having SiliconAid Solutions available to help us improve our capability will be helpful.
We would recommend SiliconAid Solutions, Inc. DFT services to any company needing expert, unbiased, and independent DFT advice. We have found SiliconAid Solutions, Inc. personnel to be very knowledgeable in all areas of test and DFT techniques and design integration.
We would not hesitate to recommend SiliconAid Solutions, Inc. services to any company needing DFT expertise.